// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: otp_ctrl

  // Top level dut name (sv module).
  dut: otp_ctrl

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: ${instance_vlnv("lowrisc:dv:otp_ctrl_sim:0.1")}

  // Testplan hjson file.
  testplan: "{self_dir}/../data/otp_ctrl_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{self_dir}/../data/otp_ctrl.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Config files to get the correct flags for crypto_dpi_prince
                "{proj_root}/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"]

  build_modes: [
    // Sim mode that enables build randomization. See the `build_seed` mode
    // defined in `hw/dv/tools/dvsim/common_modes.hjson` for more details.
    {
      name: build_seed
      pre_build_cmds: ["cd {proj_root} && ./util/design/gen-otp-mmap.py --seed {seed} --topname ${topname}"]
      is_sim_mode: 1
    }
  ]

  // Add additional tops for simulation.
  sim_tops: ["otp_ctrl_bind", "otp_ctrl_cov_bind",
             "sec_cm_prim_sparse_fsm_flop_bind",
             "sec_cm_prim_count_bind",
             "sec_cm_prim_double_lfsr_bind",
             "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Add OTP_CTRL specific exclusion files.
  vcs_cov_excl_files: ["{self_dir}/cov/otp_ctrl_cov_unr_excl.el",
                       "{self_dir}/cov/otp_ctrl_cov_fsm_unr_excl.el"]

  overrides: [
    {
      name: default_vcs_cov_cfg_file
      value: "-cm_hier {dv_root}/tools/vcs/cover.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/otp_ctrl_cover.cfg"
    }
  ]

  // Default UVM test and seq class name.
  uvm_test: otp_ctrl_base_test
  uvm_test_seq: otp_ctrl_base_vseq

  run_opts: ["+cdc_instrumentation_enabled=1"]

  // List of test specifications.
  tests: [
    {
      name: otp_ctrl_wake_up
      uvm_test_seq: otp_ctrl_wake_up_vseq
      run_opts: ["+en_scb=0"]
      reseed: 1
    }

    {
      name: otp_ctrl_smoke
      uvm_test_seq: otp_ctrl_smoke_vseq
    }

    {
      name: otp_ctrl_partition_walk
      uvm_test_seq: otp_ctrl_partition_walk_vseq
      reseed: 1
    }

    {
      name: otp_ctrl_low_freq_read
      uvm_test_seq: otp_ctrl_low_freq_read_vseq
      reseed: 1
    }

    {
      name: otp_ctrl_init_fail
      uvm_test_seq: otp_ctrl_init_fail_vseq
      reseed: 300
    }
    {
      name: otp_ctrl_background_chks
      uvm_test_seq: otp_ctrl_background_chks_vseq
      reseed: 10
    }

    {
      name: otp_ctrl_parallel_lc_req
      uvm_test_seq: otp_ctrl_parallel_lc_req_vseq
      run_opts: ["+zero_delays=1"]
    }

    {
      name: otp_ctrl_parallel_lc_esc
      uvm_test_seq: otp_ctrl_parallel_lc_esc_vseq
      reseed: 200
    }

    {
      name: otp_ctrl_dai_lock
      uvm_test_seq: otp_ctrl_dai_lock_vseq
    }

    {
      name: otp_ctrl_dai_errs
      uvm_test_seq: otp_ctrl_dai_errs_vseq
    }

    {
      name: otp_ctrl_check_fail
      uvm_test_seq: otp_ctrl_check_fail_vseq
    }

    {
      name: otp_ctrl_macro_errs
      uvm_test_seq: otp_ctrl_macro_errs_vseq
    }

    {
      name: otp_ctrl_parallel_key_req
      uvm_test_seq: otp_ctrl_parallel_key_req_vseq
    }

    {
      name: otp_ctrl_regwen
      uvm_test_seq: otp_ctrl_regwen_vseq
      // This test is to check reg programming is gated when direct_access_regwen=0
      // Thus this test is timing sensitive
      run_opts: ["+zero_delays=1"]
    }

    {
      name: otp_ctrl_test_access
      uvm_test_seq: otp_ctrl_test_access_vseq
    }

    {
      name: "{name}_stress_all_with_rand_reset"
      reseed: 100
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["otp_ctrl_smoke"]
    }
  ]
}
